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VHDL modelling and asic design of a shortest-path processor core for network routing

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Bibliographic Details
Main Author: Teoh, Giap Seng
Format: Thesis
Published: 2003
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/42788/
http://libraryopac.utm.my/client/en_AU/main/search/detailnonmodal/ent:$002f$002fSD_ILS$002f0$002fSD_ILS:360530/one?qu=VHDL+modelling+and+asic+design+of+a+shortest-path+processor+core+for+network+routing
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id my.utm.42788
record_format eprints
spelling my.utm.427882017-08-30T02:18:41Z http://eprints.utm.my/id/eprint/42788/ VHDL modelling and asic design of a shortest-path processor core for network routing Teoh, Giap Seng TK Electrical engineering. Electronics Nuclear engineering 2003 Thesis NonPeerReviewed Teoh, Giap Seng (2003) VHDL modelling and asic design of a shortest-path processor core for network routing. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. http://libraryopac.utm.my/client/en_AU/main/search/detailnonmodal/ent:$002f$002fSD_ILS$002f0$002fSD_ILS:360530/one?qu=VHDL+modelling+and+asic+design+of+a+shortest-path+processor+core+for+network+routing
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Teoh, Giap Seng
VHDL modelling and asic design of a shortest-path processor core for network routing
format Thesis
author Teoh, Giap Seng
author_facet Teoh, Giap Seng
author_sort Teoh, Giap Seng
title VHDL modelling and asic design of a shortest-path processor core for network routing
title_short VHDL modelling and asic design of a shortest-path processor core for network routing
title_full VHDL modelling and asic design of a shortest-path processor core for network routing
title_fullStr VHDL modelling and asic design of a shortest-path processor core for network routing
title_full_unstemmed VHDL modelling and asic design of a shortest-path processor core for network routing
title_sort vhdl modelling and asic design of a shortest-path processor core for network routing
publishDate 2003
url http://eprints.utm.my/id/eprint/42788/
http://libraryopac.utm.my/client/en_AU/main/search/detailnonmodal/ent:$002f$002fSD_ILS$002f0$002fSD_ILS:360530/one?qu=VHDL+modelling+and+asic+design+of+a+shortest-path+processor+core+for+network+routing
_version_ 1643650999954440192
score 13.18916

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