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Modeling router hotspots on network-on-chip

A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs...

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Main Authors: Junos, S. A. M., Marsono, Muhammad Nadzir, Ibrahim, Izzeldin, Abdel, Mohamed
Format: Book Section
Published: IEEE 2011
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://eprints.utm.my/id/eprint/29470/
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5745953
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spelling my.utm.294702017-02-04T07:47:32Z http://eprints.utm.my/id/eprint/29470/ Modeling router hotspots on network-on-chip Junos, S. A. M. Marsono, Muhammad Nadzir Ibrahim, Izzeldin Abdel, Mohamed TK Electrical engineering. Electronics Nuclear engineering A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs among latency, area, and power consumption. Hence, analytical modeling is an important step for early NoC design. This paper presents a novel top-down approach router model, and utilizes this model for analysis mesh NoC performance measured in terms of throughput, average of queue size, efficiency, loss and waiting time. The model is used also to represent utilization of NoC infrastructure resources. IEEE 2011 Book Section PeerReviewed Junos, S. A. M. and Marsono, Muhammad Nadzir and Ibrahim, Izzeldin and Abdel, Mohamed (2011) Modeling router hotspots on network-on-chip. In: 2011 13th International Conference on Advanced Communication Technology (ICACT). IEEE, Korea, pp. 896-900. ISBN 978-895519155-4 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5745953
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Junos, S. A. M.
Marsono, Muhammad Nadzir
Ibrahim, Izzeldin
Abdel, Mohamed
Modeling router hotspots on network-on-chip
description A Network-on-Chip (NoC) is a new paradigm in complex System-on-Chip (SoC) designs that provides efficient on-chip communication architecture. It offers scalable communication to SoC and allows decoupling of communication and computation. In NoC, design space exploration is critical due to trade-offs among latency, area, and power consumption. Hence, analytical modeling is an important step for early NoC design. This paper presents a novel top-down approach router model, and utilizes this model for analysis mesh NoC performance measured in terms of throughput, average of queue size, efficiency, loss and waiting time. The model is used also to represent utilization of NoC infrastructure resources.
format Book Section
author Junos, S. A. M.
Marsono, Muhammad Nadzir
Ibrahim, Izzeldin
Abdel, Mohamed
author_facet Junos, S. A. M.
Marsono, Muhammad Nadzir
Ibrahim, Izzeldin
Abdel, Mohamed
author_sort Junos, S. A. M.
title Modeling router hotspots on network-on-chip
title_short Modeling router hotspots on network-on-chip
title_full Modeling router hotspots on network-on-chip
title_fullStr Modeling router hotspots on network-on-chip
title_full_unstemmed Modeling router hotspots on network-on-chip
title_sort modeling router hotspots on network-on-chip
publisher IEEE
publishDate 2011
url http://eprints.utm.my/id/eprint/29470/
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5745953
_version_ 1643648305084760064
score 13.188455

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