Numerical simulation analysis of CMOS compatible process of 50nm vertical single and double gate MOSFET

• Main Authors: Saad, Ismail, Ismail, Razali
• Format: Conference or Workshop Item
• Published: 2007
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/14249/

Vertical MOSFET's have been proposed in the roadmap of semiconductor as a candidate for sub-100 nm CMOS technologies. In this paper, unique architecture of single and double gate vertical NMOS transistor is proposed that retained its CMOS compatibility. The MOSFET was fabricated by using obliqu...