A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models

• Main Authors: Fujiwara, Hideo, Iwata, Hiroyuki, Yoneda, Tomokazu, Ooi, Chia Yee
• Format: Article
• Published: Institute of Electrical and Electronics Engineers 2008
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.utm.my/id/eprint/12802/; http://dx.doi.org/10.1109/TCAD.2008.927765

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the tk notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclica...