A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transist...

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Main Authors: Lee, Shing Jie, Ruslan, Siti Hawa
Format: Article
Language:English
Published: UTHM 2018
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Online Access:http://eprints.uthm.edu.my/2853/1/AJ%202019%20%2847%29.pdf
http://eprints.uthm.edu.my/2853/
https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/2126
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spelling my.uthm.eprints.28532021-11-16T03:00:50Z http://eprints.uthm.edu.my/2853/ A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method Lee, Shing Jie Ruslan, Siti Hawa QA75-76.95 Calculating machines Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps. UTHM 2018 Article PeerReviewed text en http://eprints.uthm.edu.my/2853/1/AJ%202019%20%2847%29.pdf Lee, Shing Jie and Ruslan, Siti Hawa (2018) A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method. International Journal of Integrated Engineering, 10 (3). pp. 20-26. ISSN 2229-838X https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/2126
institution Universiti Tun Hussein Onn Malaysia
building UTHM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tun Hussein Onn Malaysia
content_source UTHM Institutional Repository
url_provider http://eprints.uthm.edu.my/
language English
topic QA75-76.95 Calculating machines
spellingShingle QA75-76.95 Calculating machines
Lee, Shing Jie
Ruslan, Siti Hawa
A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
description Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps.
format Article
author Lee, Shing Jie
Ruslan, Siti Hawa
author_facet Lee, Shing Jie
Ruslan, Siti Hawa
author_sort Lee, Shing Jie
title A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
title_short A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
title_full A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
title_fullStr A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
title_full_unstemmed A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
title_sort 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method
publisher UTHM
publishDate 2018
url http://eprints.uthm.edu.my/2853/1/AJ%202019%20%2847%29.pdf
http://eprints.uthm.edu.my/2853/
https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/2126
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score 13.211869