A 2x2 bit multiplier using hybrid 13t full adder with vedic mathematics method

• Main Authors: Lee, Shing Jie, Ruslan, Siti Hawa
• Format: Article
• Language: English
• Published: UTHM 2018
• Subjects: QA75-76.95 Calculating machines
• Online Access: http://eprints.uthm.edu.my/2853/1/AJ%202019%20%2847%29.pdf; http://eprints.uthm.edu.my/2853/; https://publisher.uthm.edu.my/ojs/index.php/ijie/article/view/2126

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps.