Design of Gain Booster for Sample and Hold Stage of High Speed-Low Power Pipelined Analog-To-Digital Converter
This paper presents the full custom design of an operational transconductance amplifier (OTA) for the sample and hold (SHA) stage of a 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) implemented in a TSMC 0.35μm CMOS process. The OTA chosen for this design is folded cascode with gain boos...
Saved in:
Main Author: | Jali, Mohd Hafiz |
---|---|
Format: | Article |
Language: | English |
Published: |
Penerbit UTeM
2013
|
Subjects: | |
Online Access: | http://eprints.utem.edu.my/id/eprint/9110/1/Design_of_Gain_Booster_for_Sample_and_Hold_Stage_of_High_Speed-Low_Power_Pipelined_Analog-To-Digital_Converter.pdf http://eprints.utem.edu.my/id/eprint/9110/ http://jtec.utem.edu.my/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
A 10-bit 50 mega-samples-per-second pipelined analog-to-digital converter
by: Yusoff, Yuzman
Published: (2010) -
Dual sampling sigma delta analog to digital converter
by: Mohd Isa, Maryam, et al.
Published: (2012) -
Digital-to-analog converter
by: Ma, Li Ya, et al.
Published: (2011) -
High speed – energy efficient successive approximation analog to digital converter using tri-level switching
by: Sarafi, Sahar
Published: (2015) -
Development of a 2-digit multi valued analog-to-digital converter
by: Farhana, Soheli, et al.
Published: (2012)