A reliable PUF in a dual function SRAM
The Internet of Things (IoTs) employs resource-constrained sensor nodes for sensing and processing data that require robust, lightweight cryptographic primitives. The SRAM Physical Unclonable Function (SRAM-PUF) is a potential candidate for secure key generation. An SRAM-PUF is able to generate rand...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier B.V.
2019
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| Subjects: | |
| Online Access: | http://eprints.utem.edu.my/id/eprint/24066/2/2019_A%20reliable%20PUF%20in%20a%20dual%20function%20SRAM.pdf http://eprints.utem.edu.my/id/eprint/24066/ https://www.sciencedirect.com/science/article/pii/S0167926018304747?via%3Dihub https://doi.org/10.1016/j.vlsi.2019.06.001 |
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| Summary: | The Internet of Things (IoTs) employs resource-constrained sensor nodes for sensing and processing data that require robust, lightweight cryptographic primitives. The SRAM Physical Unclonable Function (SRAM-PUF) is a potential candidate for secure key generation. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values by exploiting intrinsic manufacturing process variations. The reuse of the available on-chip SRAM memory in a system as a PUF might achieve useful cost efficiency. However, as CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable start-up values for an SRAM-PUF. In this paper, the on-chip memory in the ARM architecture has been used as a case study to investigate reliability in an SRAM-PUF. We show that the bit probability in a 32-bit ARM instruction cache has a predictable pattern and hence predictable aging. Therefore, we propose using an instruction cache as a PUF to save silicon area. Furthermore, we propose a bit selection technique to mitigate the NBTI effect. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction circuitry is about 6 × smaller compared to that without a bit selection technique. |
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