Current Steering Digital Analog Converter (DAC) Using Partial Binary Tree Network (PBTN)

• Main Author: Mohammad Alias, Mohd Azim
• Format: Monograph
• Language: English
• Published: Universiti Sains Malaysia 2018
• Subjects: T Technology; TK Electrical Engineering. Electronics. Nuclear Engineering
• Online Access: http://eprints.usm.my/53324/1/Current%20Steering%20Digital%20Analog%20Converter%20%28Dac%29%20Using%20Partial%20Binary%20Tree%20Network%20%28Pbtn%29_Mohd%20Azim%20Mohammad%20Alias_E3_2018.pdf; http://eprints.usm.my/53324/

Digital-to-analog converters (DACs) are essential operations in many digital systems which require data converters from digital form to analog form. DAC rely on the matched component to perform data conversion. However, matched components are nearly impossible to fabricate, there will always be mismatch errors which cause discrepancies between the desired value and designed value. Dynamic Element Matching (DEM) is commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering the DAC block. Using this technique, the time averages of the equivalent components at each of the component positions are equal or nearly equal to reduce the effects of component mismatches in electronic circuits. A complicated encoding is usually necessary for conventional DEM encoders which will lead to many of switch transitions happens at the same time and it will cause glitches in the output signal. Previous research is able to increase the boundaries of Partial Binary Tree Network (PBTN) to 8-Bits. In this research, DEM algorithm is used, known as Partial Binary Tree Network (PBTN) that been proposed from previous research that aims to push the boundaries of past research from 8-bits to 10-bits. Besides, in this research, the Current Controlled Current Source (CCCS) used to magnify the output current in previous research is replaced with operating amplifier. PBTN is used because it has lower complexity circuit and fewer glitches produce at the output signal. This thesis reports the simulation of 8-bit 1-MSB with DNL of -0.550197255 LSB, INL of 0.752682 LSB, the power consumption of 16.7 mW and for 10-Bit 1-MSB with DNL of -0.535378495 LSB, INL of 0.955382 LSB, the power consumption of 66.31 mW. Power consumption in this research achieved much lower than the previous research.