Enhancement Of Methodology And Definition For Serial Protocol Electrical Specification Compatibility For Non-Compliant Fpga

• Main Author: Tan , Shwu Fei
• Format: Thesis
• Language: English
• Published: 2014
• Subjects: TK Electrical Engineering. Electronics. Nuclear Engineering
• Online Access: http://eprints.usm.my/40919/1/TAN_SHWU_FEI_24_pages.pdf; http://eprints.usm.my/40919/

A new methodology and definition for a clearer compatibility for middle-range and low-end Field Programmable Gate Array (FPGA) transceiver is presented in this research. It has been a big challenge to balance between cost and performance in order to meet the full industrial protocol specification for middle-range and low-end FPGA. When the products are not able to achieve full protocol specification, the company will still market these products and claim that they are compatible. With this kind of situation, there are no guidelines can be followed; hence, users will not have confidence to design the product. In this research, a clearer compatible specification is obtained to provide channel loss requirement by extracting the timing margin at different test points. The research also ensures that quantifiable margin is allocated when compatible specification is defined. The middle-range FPGA that used in this research is Arria V GT device to define the new compatible specification with reference to IEEE 10GBASE-KR protocol where the compatible specification is used for board-based 10Gbps applications. The methodology used is by extracting the timing margin and find out the channel loss from 3 different test points which include Scenario 1) Transmitter is Arria V GT; Receiver is Compliant Receiver, Scenario 2) Transmitter and Receiver are from Arria V GT and Scenario 3) Transmitter is Compliant Transmitter; Receiver is from Arria V GT. 16-ps of timing margin is obtained from the research, while the channel loss for Scenario 1 is -16dB, Scenario 2 is -12dB and Scenario 3 is -17dB with error-free transfer for BER10-12 .