FPGA implementation of handwritten number recognition using artificial neural network
Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The propo...
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Online Access: | http://psasir.upm.edu.my/id/eprint/78077/1/FPGA%20implementation%20of%20handwritten%20number%20recognition%20using%20artificial%20neural%20network.pdf http://psasir.upm.edu.my/id/eprint/78077/ |
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my.upm.eprints.780772020-06-02T03:10:38Z http://psasir.upm.edu.my/id/eprint/78077/ FPGA implementation of handwritten number recognition using artificial neural network Mittal, Harsh Sharma, Abhishek Perumal, Thinagaran Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The proposed ANN was verified and compared with several ANN networks on MATLAB, which gave the accuracy of about 99.38%. This network was implemented on Xilinx Zybo board XC7Z010CLG400-1. The total area covered by the IP block is 27.9%. The IP created is efficient and uses fewer resources thus suitable for other embedded applications. IEEE 2019 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/78077/1/FPGA%20implementation%20of%20handwritten%20number%20recognition%20using%20artificial%20neural%20network.pdf Mittal, Harsh and Sharma, Abhishek and Perumal, Thinagaran (2019) FPGA implementation of handwritten number recognition using artificial neural network. In: 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), 15-18 Oct. 2019, Osaka, Japan. (pp. 1010-1011). 10.1109/GCCE46687.2019.9015236 |
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Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The proposed ANN was verified and compared with several ANN networks on MATLAB, which gave the accuracy of about 99.38%. This network was implemented on Xilinx Zybo board XC7Z010CLG400-1. The total area covered by the IP block is 27.9%. The IP created is efficient and uses fewer resources thus suitable for other embedded applications. |
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Conference or Workshop Item |
author |
Mittal, Harsh Sharma, Abhishek Perumal, Thinagaran |
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Mittal, Harsh Sharma, Abhishek Perumal, Thinagaran FPGA implementation of handwritten number recognition using artificial neural network |
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Mittal, Harsh Sharma, Abhishek Perumal, Thinagaran |
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Mittal, Harsh |
title |
FPGA implementation of handwritten number recognition using artificial neural network |
title_short |
FPGA implementation of handwritten number recognition using artificial neural network |
title_full |
FPGA implementation of handwritten number recognition using artificial neural network |
title_fullStr |
FPGA implementation of handwritten number recognition using artificial neural network |
title_full_unstemmed |
FPGA implementation of handwritten number recognition using artificial neural network |
title_sort |
fpga implementation of handwritten number recognition using artificial neural network |
publisher |
IEEE |
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2019 |
url |
http://psasir.upm.edu.my/id/eprint/78077/1/FPGA%20implementation%20of%20handwritten%20number%20recognition%20using%20artificial%20neural%20network.pdf http://psasir.upm.edu.my/id/eprint/78077/ |
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