FPGA implementation of handwritten number recognition using artificial neural network
Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The propo...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2019
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| Online Access: | http://psasir.upm.edu.my/id/eprint/78077/1/FPGA%20implementation%20of%20handwritten%20number%20recognition%20using%20artificial%20neural%20network.pdf http://psasir.upm.edu.my/id/eprint/78077/ |
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| Summary: | Implementation of Deep Learning and Machine Learning Algorithms is always a challenge as they consume a lot of resources and power. In this paper, we have presented a very simple yet efficient way for creating an IP (intellectual property) core for Handwritten Number Recognition for FPGAs. The proposed ANN was verified and compared with several ANN networks on MATLAB, which gave the accuracy of about 99.38%. This network was implemented on Xilinx Zybo board XC7Z010CLG400-1. The total area covered by the IP block is 27.9%. The IP created is efficient and uses fewer resources thus suitable for other embedded applications. |
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