Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus

• Main Authors: Mai, Yoong Ching, Ang, Tun Boon, Chin, Kock Yeong, Rokhani, Fakhrul Zaman
• Format: Conference or Workshop Item
• Language: English
• Published: IEEE 2010
• Online Access: http://psasir.upm.edu.my/id/eprint/68598/1/Interconnect%20area%2C%20delay%20and%20area-delay%20optimization%20for%20multi-level%20signaling%20on-chip%20bus.pdf; http://psasir.upm.edu.my/id/eprint/68598/

In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MC...