Design of a sub-picosecond jitter with adjustable-range CMOS delay-locked loop for high-speed and low-power applications

• Main Authors: Abdulrazzaq, Bilal Isam, Ibrahim, Omar J., Kawahito, Shoji, Mohd Sidek, Roslina, Shafie, Suhaidi, Md Yunus, Nurul Amziah, Lee, Lini, Abdul Halin, Izhal
• Format: Article
• Language: English
• Published: MDPI 2016
• Online Access: http://psasir.upm.edu.my/id/eprint/55975/1/55975.pdf; http://psasir.upm.edu.my/id/eprint/55975/; http://www.mdpi.com/1424-8220/16/10/1593

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...