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Design of a reconfigurable FFT processor using multi-objective genetic algorithm

This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make su...

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Main Authors: Pang, Jia Hong, Sulaiman, Nasri
Format: Conference or Workshop Item
Language:English
Published: IEEE 2010
Online Access:http://psasir.upm.edu.my/id/eprint/47776/1/Design%20of%20a%20reconfigurable%20FFT%20processor%20using%20multi-objective%20genetic%20algorithm.pdf
http://psasir.upm.edu.my/id/eprint/47776/
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spelling my.upm.eprints.477762016-07-15T05:24:30Z http://psasir.upm.edu.my/id/eprint/47776/ Design of a reconfigurable FFT processor using multi-objective genetic algorithm Pang, Jia Hong Sulaiman, Nasri This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor. IEEE 2010 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/47776/1/Design%20of%20a%20reconfigurable%20FFT%20processor%20using%20multi-objective%20genetic%20algorithm.pdf Pang, Jia Hong and Sulaiman, Nasri (2010) Design of a reconfigurable FFT processor using multi-objective genetic algorithm. In: International Conference on Intelligent and Advanced Systems (ICIAS 2010), 15-17 June 2010, Kuala Lumpur, Malaysia. . 10.1109/ICIAS.2010.5716157
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor.
format Conference or Workshop Item
author Pang, Jia Hong
Sulaiman, Nasri
spellingShingle Pang, Jia Hong
Sulaiman, Nasri
Design of a reconfigurable FFT processor using multi-objective genetic algorithm
author_facet Pang, Jia Hong
Sulaiman, Nasri
author_sort Pang, Jia Hong
title Design of a reconfigurable FFT processor using multi-objective genetic algorithm
title_short Design of a reconfigurable FFT processor using multi-objective genetic algorithm
title_full Design of a reconfigurable FFT processor using multi-objective genetic algorithm
title_fullStr Design of a reconfigurable FFT processor using multi-objective genetic algorithm
title_full_unstemmed Design of a reconfigurable FFT processor using multi-objective genetic algorithm
title_sort design of a reconfigurable fft processor using multi-objective genetic algorithm
publisher IEEE
publishDate 2010
url http://psasir.upm.edu.my/id/eprint/47776/1/Design%20of%20a%20reconfigurable%20FFT%20processor%20using%20multi-objective%20genetic%20algorithm.pdf
http://psasir.upm.edu.my/id/eprint/47776/
_version_ 1643833979250409472
score 13.160551

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