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VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language...

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Main Authors: Emilliano, Chakrabarty, C.K., Ghani, A.B.A., Ramasamy, A.K.
Format: Conference Paper
Language:en_US
Published: 2017
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spelling my.uniten.dspace-57262017-12-14T04:30:30Z VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA Emilliano Chakrabarty, C.K. Ghani, A.B.A. Ramasamy, A.K. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. © 2010 IEEE. 2017-12-08T06:45:44Z 2017-12-08T06:45:44Z 2010 Conference Paper 10.1109/ICSGRC.2010.5562530 en_US Proceedings - ICSGRC 2010: 2010 IEEE Control and System Graduate Research Colloquium 2010, Article number 5562530, Pages 14-19
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
language en_US
description This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in high voltage underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The output signals of peak detector block, 64 bit BCD counter with reset block and reset automatic block is processed using reset automatic block and 64 bit latch block for keep output data in LCD to constant when the 64 bit BCD counter block is reset and return to zero again until update new data again. The combination of all blocks of PD detection circuit system is tested by using ISE simulator. In the next stage, this method will be implemented on a lab simulation scale for testing and validation. © 2010 IEEE.
format Conference Paper
author Emilliano
Chakrabarty, C.K.
Ghani, A.B.A.
Ramasamy, A.K.
spellingShingle Emilliano
Chakrabarty, C.K.
Ghani, A.B.A.
Ramasamy, A.K.
VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
author_facet Emilliano
Chakrabarty, C.K.
Ghani, A.B.A.
Ramasamy, A.K.
author_sort Emilliano
title VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_short VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_full VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_fullStr VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_full_unstemmed VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA
title_sort vhdl simulation of reset automatic block, 64 bit latch block, and test complete blocks for pd detection circuit system using fpga
publishDate 2017
_version_ 1644493759514148864
score 13.214268

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