Simulation of fabrication process VDMOSFET transistor using Silvaco software

Taguchi Method is being applied in to find the sequence of dominance for factors that determine the performance of a VDMOSFET power transistor. The main objective of this project is to optimize the trench depth, trench width, epitaxial resistivity and thickness in power VDMOSFET so as to obtain high...

Full description

Saved in:
Bibliographic Details
Main Authors: Abdullah, H., Jurait, J., Lennie, A., Nopiah, Z.M., Ahmad, I.
Format:
Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5261
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.uniten.dspace-5261
record_format dspace
spelling my.uniten.dspace-52612017-11-15T02:57:07Z Simulation of fabrication process VDMOSFET transistor using Silvaco software Abdullah, H. Jurait, J. Lennie, A. Nopiah, Z.M. Ahmad, I. Taguchi Method is being applied in to find the sequence of dominance for factors that determine the performance of a VDMOSFET power transistor. The main objective of this project is to optimize the trench depth, trench width, epitaxial resistivity and thickness in power VDMOSFET so as to obtain high breakdown voltage but low on-resistance. Optimization of trench depth, trench width, epitaxial resistivity and epitaxial thickness are based on L9 array. Taguchi Method was being applied to reduce development time and to ensure that the products are in the acceptable quality range. The robust nature of Taguchi Method pointed out the most dominant factors that will determine the performance and characteristics of the power transistor. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the fabrication and also simulating the electrical performance of the transistors. The parameters under investigation were the threshold voltage (VTH), breakdown voltage (BV) and on-resistance (RON). The data produced from the experiments were used to determine the sequence of dominance for the factors involved in the transistor's characteristics. Taguchi suggests that to analyzing Signal-to-Noise ratios (S/N) by using conceptual approach that involves graphing the effects and visually identifying the factors that show to be significant. The slopes of the lines also show the relative influence of the factor to the variability of results. The Pareto ANOVA method is used to analyze the data for process optimization. This is a quick and easy method for analyzing results of parameter design that does not require an ANOVA table and does not use F-tests. This method enables the significance of factors to be evaluated by Pareto type analysis. It also allows the optimal levels of factors to be obtained. From the experimental results, the trench depth, epitaxial resistance, and epitaxial are significant factors toward breakdown voltage and on-resistance in n-channel VDMOSFET. © EuroJournals Publishing, Inc. 2009. 2017-11-15T02:57:07Z 2017-11-15T02:57:07Z 2009 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5261
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description Taguchi Method is being applied in to find the sequence of dominance for factors that determine the performance of a VDMOSFET power transistor. The main objective of this project is to optimize the trench depth, trench width, epitaxial resistivity and thickness in power VDMOSFET so as to obtain high breakdown voltage but low on-resistance. Optimization of trench depth, trench width, epitaxial resistivity and epitaxial thickness are based on L9 array. Taguchi Method was being applied to reduce development time and to ensure that the products are in the acceptable quality range. The robust nature of Taguchi Method pointed out the most dominant factors that will determine the performance and characteristics of the power transistor. ATHENA and ATLAS module of SILVACO software are the tools used in simulating the fabrication and also simulating the electrical performance of the transistors. The parameters under investigation were the threshold voltage (VTH), breakdown voltage (BV) and on-resistance (RON). The data produced from the experiments were used to determine the sequence of dominance for the factors involved in the transistor's characteristics. Taguchi suggests that to analyzing Signal-to-Noise ratios (S/N) by using conceptual approach that involves graphing the effects and visually identifying the factors that show to be significant. The slopes of the lines also show the relative influence of the factor to the variability of results. The Pareto ANOVA method is used to analyze the data for process optimization. This is a quick and easy method for analyzing results of parameter design that does not require an ANOVA table and does not use F-tests. This method enables the significance of factors to be evaluated by Pareto type analysis. It also allows the optimal levels of factors to be obtained. From the experimental results, the trench depth, epitaxial resistance, and epitaxial are significant factors toward breakdown voltage and on-resistance in n-channel VDMOSFET. © EuroJournals Publishing, Inc. 2009.
format
author Abdullah, H.
Jurait, J.
Lennie, A.
Nopiah, Z.M.
Ahmad, I.
spellingShingle Abdullah, H.
Jurait, J.
Lennie, A.
Nopiah, Z.M.
Ahmad, I.
Simulation of fabrication process VDMOSFET transistor using Silvaco software
author_facet Abdullah, H.
Jurait, J.
Lennie, A.
Nopiah, Z.M.
Ahmad, I.
author_sort Abdullah, H.
title Simulation of fabrication process VDMOSFET transistor using Silvaco software
title_short Simulation of fabrication process VDMOSFET transistor using Silvaco software
title_full Simulation of fabrication process VDMOSFET transistor using Silvaco software
title_fullStr Simulation of fabrication process VDMOSFET transistor using Silvaco software
title_full_unstemmed Simulation of fabrication process VDMOSFET transistor using Silvaco software
title_sort simulation of fabrication process vdmosfet transistor using silvaco software
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5261
_version_ 1644493631375015936
score 13.214268