Process parameters optimization of 14nm p-type MOSFET using 2-D analytical modeling
Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulator-conductor that were used includes a high-k material and a metal gate w...
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| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | en_US |
| Published: |
2017
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| Summary: | Simulations of a computer-generated downscaled device at 14nm gate length of p-type MOSFET is conferred in this paper. The device is scaled down from a 32nm transistor which is from the former research. A combination of insulator-conductor that were used includes a high-k material and a metal gate where in this research, Hafnium Dioxide (HfO2) is used as high-k material and Tungsten Silicide (WSi2) is used as a metal gate. A 14nm p-type transistor was virtually fabricated using ATHENA module and characterized its performance evaluation using ATLAS module in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The scaled down device is then optimized through process parameter variability using Taguchi Method. The objective is to find the best combination of fabrication parameter in order to achieve the targeted value of threshold voltage (VTH) and leakage current (IOFF) that are predicted by International Technology Roadmap for Semiconductors (ITRS) 2013. The results show that the ideal value for VTH and IOFF are 0.248635±12.7% V and 5.26x10-12 A/um respectively and the results were achieved according to the ITRS specification. |
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