LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

• Main Authors: Islam S.Z., Ali M.A.M.
• Other Authors: 55432804400
• Format: Conference paper
• Published: Institute of Electrical and Electronics Engineers Inc. 2023
• Subjects: Cost reduction; Hardware; Benchmark circuit; Circuit under test; Fault coverages; Hardware overheads; Hybrid patterns; Low hardware costs; Low-power dissipation; Switching activities; Built-in self test

This paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selecte...