High performance FPGA architecture for dual mode processor of Integer Haar Lifting-based Wavelet Transform

• Main Authors: Shahadi H.I., Jidin R., Way W.H.
• Other Authors: 54956597100
• Format: Article
• Published: 2023
• Subjects: Dual mode processor; Field programmable gate array (FPGA); Haar filter; Integer to integer (Int2Int) Wavelet; Lifting wavelet transform (LWT)

Discrete Wavelet Transform (DWT) becomes a major part for many applications. Fast, low area, and low power consumption hardware for DWT is necessary for some new technologies such as OFDM transceiver and wireless multimedia sensor networks. This paper presents efficient dual mode (decomposition and reconstruction) Integer Haar Lifting Wavelet Transform (IHLWT) architecture. The proposed architecture reduces the hardware requirements by exploiting the arithmetic operations redundancy which is involved in IHLWT computations. It is multiplier-free and it performs IHLWT with only a single adder and subtractor which have reconfigurable input buses to perform decomposition and reconstruction transformations. IEEE standard VHDL has been used to develop the proposed processor. This makes the design vendor independent and therefore easily portable across FPGA devices from multiple vendors. The generic design is flexible and can perform any arbitrary signal length. The synthesis of the processor showed that it requires low number of CLB-slices and low power consumption with high operating-frequency for various Xilinx FPGA devices. The processor has been successfully implemented and tested on Xilinx Spartan6-SP601 Evaluation Board. The implemented hardware has been tested in real time by using many recording audio signals. All the implemented hardware results were identical 100% with IHLWT software results. � 2013 Praise Worthy Prize S.r.l. - All rights reserved.