Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method
This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabricat...
Saved in:
Main Authors: | , , , , , , |
---|---|
其他作者: | |
格式: | Conference Paper |
出版: |
Institute of Electrical and Electronics Engineers Inc.
2023
|
标签: |
添加标签
没有标签, 成为第一个标记此记录!
|