Soft Error Analysis On Digital Circuit

• Main Author: Nur Fa’iqah, Sabtu
• Format: Final Year Project Report
• Language: English; English
• Published: Universiti Malaysia Sarawak (UNIMAS) 2023
• Subjects: T Technology (General)
• Online Access: http://ir.unimas.my/id/eprint/43020/1/Nur%20Faiqah%20%2824pgs%29.pdf; http://ir.unimas.my/id/eprint/43020/2/Nur%20Faiqah%20%28Fulltext%29.pdf; http://ir.unimas.my/id/eprint/43020/

Soft errors, also known as Single Event Upsets (SEUs), occur due to the impact of energetic particles originating from sources such as cosmic rays, radioactive decay, or particle strikes. These incidents result in radiation strikes that can disrupt the charge in a memory cell, flip-flop, or register, leading to a flip or reversal of the data state. This study focuses on analysing the occurrence of soft errors in digital circuits. To investigate this phenomenon, an 8-bit Kogge-Stone adder circuit was constructed using VHDL code in Quartus II as part of this project. Additionally, a memory latch configuration known as C-element was designed to assess the impact of soft errors on the memory component within the adder system. Moreover, the goal was to find effective mitigation techniques that address soft errors without affecting the overall reliability of the circuit. For this particular project, one method that was implemented involved error detection and correction. Throughout the project, the system was able to successfully identify and mitigate the soft errors, ensuring the integrity of the data and the proper functioning of the adder system.