Implementation of Verilog HDL in Calculator Design with FPGA Simulation
A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtr...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020
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| Subjects: | |
| Online Access: | http://ir.unimas.my/id/eprint/33604/1/Implementation%20of%20Verilog%20HDL%20in%20Calculator.pdf http://ir.unimas.my/id/eprint/33604/ https://ieeexplore.ieee.org/document/9299337 |
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| Summary: | A calculator is a device that can be found in daily life. This paper proposed the design of a calculator using Verilog HDL. A series of synthesizable Verilog code was created and simulated on Quartus II 15.0. The design of an 8-bit calculator can solve mathematical operations such as addition, subtraction, multiplication, division, square and cube functions, square root and factorial. This calculator consists of eight-digit numbers. In this paper, among the family devices in Altera, Cyclone V was used to perform the simulation process. The outputs are shown in the RTL viewer and waveform simulation of the calculator design. The implementation of a calculator was successfully designed using Verilog HDL in terms of digit numbers and the operation of the calculator function. |
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