Analysis of Gate Poly Delayering in SOI Wafer

• Main Authors: Shahrol, Mohamaddan, Handie, Ahmataku, Emilda, Warren, Mahshuri, Yusof, Aidil Azli, Alias, Nor Hasmaliana, Abdul Manas, Kuryati, Kipli
• Format: Article
• Language: English
• Published: Universiti Teknikal Malaysia Melaka 2018
• Subjects: TJ Mechanical engineering and machinery
• Online Access: http://ir.unimas.my/id/eprint/25420/1/Analysis%20of%20Gate%20Poly%20Delayering%20in%20SOI%20Wafer%20%28abstract%29.pdf; http://ir.unimas.my/id/eprint/25420/; http://journal.utem.edu.my/index.php/jtec/index

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon...