Performance of CMOS Schmitt Trigger
This paper presents the effect of load capacitance and source voltage on performance of proposed Schmitt trigger circuit. The proposed circuit was designed based on Conventional Schmitt Trigger by manipulating the arrangement of transistors and the width-length ratio. All simulation results hav...
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Main Authors: | , , , |
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Format: | E-Article |
Language: | English |
Published: |
IEEE
2008
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Subjects: | |
Online Access: | http://ir.unimas.my/id/eprint/16596/1/Performance%20of%20CMOS%20Schmitt%20Trigger%28abstract%29.pdf http://ir.unimas.my/id/eprint/16596/ http://ieeexplore.ieee.org/document/4580818/ |
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Summary: | This paper presents the effect of load capacitance and
source voltage on performance of proposed Schmitt
trigger circuit. The proposed circuit was designed based
on Conventional Schmitt Trigger by manipulating the
arrangement of transistors and the width-length ratio. All
simulation results have been carried out based on
Microwind software on three different designs in term of
propagation delay, Energy-delay Product and hystheresis.
From the result, the proposed full swing CMOS Schmitt
Trigger was able to operate as low voltage (0.8V-1.5V). |
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