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Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity

Master of Science in Embedded Systems Design Engineering

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Bibliographic Details
Main Author: Hussein Ibrahim, Hussein
Other Authors: Muataz Hameed Salih, Al Doori, Dr.
Format: Thesis
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2017
Subjects:
Embedded computer systems
Field programmable gate arrays
Embedded system
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/72440
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spelling my.unimap-724402021-12-17T02:59:48Z Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity Hussein Ibrahim, Hussein Muataz Hameed Salih, Al Doori, Dr. Embedded computer systems Field programmable gate arrays Embedded system Master of Science in Embedded Systems Design Engineering The condition that drives a system to complete the processing of a number of functions within a given amount of time is called the real-time system. A projective missile system’s processing platforms face two major issues: high cost and structureal complexity. The system structure’s complexity is a result of various reasons that include the mechanism utilised in the system in order to perform the system functionality. This mechanism can lead to delays in data processing because various factors, such as the synchronisation of the system modules’ signals, the processing unit’s architecture, and the unit’s computational power. In order to lessen system complexity and system cost, true parallelism mechanism is applied over the embedded system, along with a concurrent structure. The FPGA platform (DE1-SoC) was used as the implementation environment for this system. This led to an enriched implemented system that had low costs. Furthermore, the system complexity is lessened since the system uses a concurrent structure. Some of the modules that are closely related to the system are implemented to support main processing module. In this system, the signals covered were in four directions. The total logic element was (5032) and total registers was (5180). The Phase Locked Loop up to (1.6) GHz was manipulated in order to allow the system cover a wide spectrum of signals with high accuracy of computing process. Furthermore, the laser projective frequency jamming system is capable of processing multiple frequencies at a time. The implementation was able to obtain acceptable levels of throughput and it also lowered the complexity. Furthermore, the structural design methodology also makes it possible for the embedded concurrent computing architecture to be scalable while the entire system grows. 2017 2021-10-14T02:09:28Z 2021-10-14T02:09:28Z Thesis http://dspace.unimap.edu.my:80/xmlui/handle/123456789/72440 en Universiti Malaysia Perlis (UniMAP) Universiti Malaysia Perlis (UniMAP) School of Computer and Communication Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Embedded computer systems
Field programmable gate arrays
Embedded system
spellingShingle Embedded computer systems
Field programmable gate arrays
Embedded system
Hussein Ibrahim, Hussein
Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
description Master of Science in Embedded Systems Design Engineering
author2 Muataz Hameed Salih, Al Doori, Dr.
author_facet Muataz Hameed Salih, Al Doori, Dr.
Hussein Ibrahim, Hussein
format Thesis
author Hussein Ibrahim, Hussein
author_sort Hussein Ibrahim, Hussein
title Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_short Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_full Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_fullStr Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_full_unstemmed Design and implementation of embedded true parallelism jammer system using FGPA-SoC for low design complexity
title_sort design and implementation of embedded true parallelism jammer system using fgpa-soc for low design complexity
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2017
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/72440
_version_ 1724609901854982144
score 13.214268

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