A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
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Institute of Electrical and Electronics Engineering (IEEE)
2009
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my.unimap-68942017-11-29T04:45:00Z A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree Hasliza, A. Rahim@Samsuddin Ab Rahman, A. A H Andaljayalakshmi, G. R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin Very large scale integrated (VLSI) Integrated circuit layout Integrated logic circuits Genetic algorithms Trees (mathematics) Integrated circuits -- Design and construction Integrated circuits Link to publisher's homepage at http://ieeexplore.ieee.org This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three different types of genetic algorithms: simple genetic algorithm (SGA), steady-state algorithm (SSGA) and adaptive genetic algorithm (AGA) are employed in order to examine their performances in converging to their global minimums. Experimental results on Microelectronics Center of North Carolina (MCNC) benchmark problems show that the developed algorithm achieves an acceptable performance quality to the slicing floorplan. Furthermore, the robustness of genetic algorithm also has been investigated in order to validate the performance stability in achieving the optimal solution for every runtime. This algorithm demonstrates that SSGA converges to the optimal result faster than SGA and AGA. Besides that, SSGA also outperforms SGA and AGA in terms of robustness. 2009-08-14T02:17:19Z 2009-08-14T02:17:19Z 2008-05 Article p.26-31 978-1-4244-1691-2 http://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4580562 http://hdl.handle.net/123456789/6894 en Proceedings of the International Conference on Computer and Communication Engineering (ICCCE 2008) Institute of Electrical and Electronics Engineering (IEEE) |
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English |
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Very large scale integrated (VLSI) Integrated circuit layout Integrated logic circuits Genetic algorithms Trees (mathematics) Integrated circuits -- Design and construction Integrated circuits |
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Very large scale integrated (VLSI) Integrated circuit layout Integrated logic circuits Genetic algorithms Trees (mathematics) Integrated circuits -- Design and construction Integrated circuits Hasliza, A. Rahim@Samsuddin Ab Rahman, A. A H Andaljayalakshmi, G. R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| description |
Link to publisher's homepage at http://ieeexplore.ieee.org |
| format |
Article |
| author |
Hasliza, A. Rahim@Samsuddin Ab Rahman, A. A H Andaljayalakshmi, G. R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin |
| author_facet |
Hasliza, A. Rahim@Samsuddin Ab Rahman, A. A H Andaljayalakshmi, G. R. Badlishah, Ahmad Wan Nur Suryani Firuz, Wan Ariffin |
| author_sort |
Hasliza, A. Rahim@Samsuddin |
| title |
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_short |
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_full |
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_fullStr |
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_full_unstemmed |
A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_sort |
genetic algorithm approach to vlsi macro cell non-slicing floorplans using binary tree |
| publisher |
Institute of Electrical and Electronics Engineering (IEEE) |
| publishDate |
2009 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/6894 |
| _version_ |
1643802700468453376 |
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13.222552 |