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Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput

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Bibliographic Details
Main Author: Poovaneswaran, Murugasan
Other Authors: Dr Muataz Hameed Salih AL-Doori
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis (UniMAP) 2016
Subjects:
FIR filter
Filter
Systolic approach
Field Programmable Gate Array (FPGA)
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42096
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spelling my.unimap-420962016-06-17T07:42:14Z Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput Poovaneswaran, Murugasan Dr Muataz Hameed Salih AL-Doori FIR filter Filter Systolic approach Field Programmable Gate Array (FPGA) Access is limited to UniMAP community. This project is about enhancing FIR filter using systolic approach for faster processing and better throughput. In signal processing, FIR filter is a filter whose impulse response is of finite duration because it settles to zero in finite time. Systolic architecture is used in this project because it will permit multiple computations for each memory access and also it can speed up the execution of compute-bound problems without increasing I/O requirements. The enhancing of FIR filter uses the Very High Speed Integrated Circuit Hardware Language (VHDL) code and the output will be displayed on the ALTERA NEEK (Nios II Embedded Evaluation Kit) board. The VHDL code plays the main role in this project. The VHDL code will be written into the Quartus software and then will be executed. The result will be displayed on the FPGA board. Finally, the performance of the design will be analysed and discussed with supervisor. 2016-06-17T07:42:14Z 2016-06-17T07:42:14Z 2015-06 Learning Object http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42096 en Universiti Malaysia Perlis (UniMAP) School of Computer and Communication Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic FIR filter
Filter
Systolic approach
Field Programmable Gate Array (FPGA)
spellingShingle FIR filter
Filter
Systolic approach
Field Programmable Gate Array (FPGA)
Poovaneswaran, Murugasan
Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
description Access is limited to UniMAP community.
author2 Dr Muataz Hameed Salih AL-Doori
author_facet Dr Muataz Hameed Salih AL-Doori
Poovaneswaran, Murugasan
format Learning Object
author Poovaneswaran, Murugasan
author_sort Poovaneswaran, Murugasan
title Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
title_short Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
title_full Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
title_fullStr Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
title_full_unstemmed Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput
title_sort enhance fir implementation on fpga using systolic approach for fast processing and better throughput
publisher Universiti Malaysia Perlis (UniMAP)
publishDate 2016
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42096
_version_ 1643799895308500992
score 13.222552

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