Cover Image

Low-power and high-performance 1-bit set Full-adder

Link to publisher's homepage at http://ijneam.unimap.edu.my/

Saved in:
Bibliographic Details
Main Authors: Paulthurai, Anbarasu, Dharmaraj, Balamurugan
Other Authors: anbarasu_003@yahoo.com
Format: Article
Language:English
Published: Universiti Malaysia Perlis 2016
Subjects:
SET
Full Adder
High-Speed
Online Access:http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41321
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.unimap-41321
record_format dspace
spelling my.unimap-413212017-11-21T03:12:30Z Low-power and high-performance 1-bit set Full-adder Paulthurai, Anbarasu Dharmaraj, Balamurugan anbarasu_003@yahoo.com SET Full Adder High-Speed Link to publisher's homepage at http://ijneam.unimap.edu.my/ An adder is an important element of all arithmetic and logic units. The recent trend in Nanotechnology is moving towards the need of the devices, which consume low power. The Single Electron Transistor (SET), distinguish by a very small device size low power dissipation, high speed and high performance, is one of the most promising nano electronics devices to replace conventional CMOS. The SET technology offers the ability to control the motion of individual electrons in the designed circuits. In this Full Adder Circuit we were used 24 SET and 14 resistors. The circuit is functioning as required for all the combination of input voltage. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in SET process technology. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. The Low-Power and High-Performance 1-Bit Set Full-Adder digital circuits have been simulated by PSPICE 9.1. 2016-04-22T08:58:57Z 2016-04-22T08:58:57Z 2013 Article International Journal of Nanoelectronics and Materials, vol.6 (2), 2013, pages 105-111 1985-5761 (Printed) 1997-4434 (Online) http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41321 en Universiti Malaysia Perlis
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic SET
Full Adder
High-Speed
spellingShingle SET
Full Adder
High-Speed
Paulthurai, Anbarasu
Dharmaraj, Balamurugan
Low-power and high-performance 1-bit set Full-adder
description Link to publisher's homepage at http://ijneam.unimap.edu.my/
author2 anbarasu_003@yahoo.com
author_facet anbarasu_003@yahoo.com
Paulthurai, Anbarasu
Dharmaraj, Balamurugan
format Article
author Paulthurai, Anbarasu
Dharmaraj, Balamurugan
author_sort Paulthurai, Anbarasu
title Low-power and high-performance 1-bit set Full-adder
title_short Low-power and high-performance 1-bit set Full-adder
title_full Low-power and high-performance 1-bit set Full-adder
title_fullStr Low-power and high-performance 1-bit set Full-adder
title_full_unstemmed Low-power and high-performance 1-bit set Full-adder
title_sort low-power and high-performance 1-bit set full-adder
publisher Universiti Malaysia Perlis
publishDate 2016
url http://dspace.unimap.edu.my:80/xmlui/handle/123456789/41321
_version_ 1643802797211123712
score 13.222552

Similar Items