Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs
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Institute of Electrical and Electronics Engineers (IEEE)
2013
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my.unimap-239932013-03-08T02:25:18Z Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs Mohd Khairuddin, Md Arshad, Dr. Raskin, Jean-Pierre, Prof. Kilchytska, Valeriya, Dr. Andrieu, François, Dr. Scheiblin, Pascal Faynot, O. Flandre, Denis, Prof. mohd.khairuddin@unimap.edu.my jean-pierre.raskin@uclouvain.be pascal.scheiblin@cea.fr Drain-induced barrier lowering (DIBL) fully depleted silicon-on-insulator (FDSOI) MOSFETs ultrathin silicon body and thin buried oxide (UTBB) MASTAR model Substrate depletion depth (T Sub) Substrate/buried oxide (BOX) interface space-charge condition Ultrathin silicon body (UTB) Link to publisher's homepage at http://ieeexplore.ieee.org/ This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL. 2013-03-08T01:50:00Z 2013-03-08T01:50:00Z 2012-01 Article IEEE Transactions on Electron Devices, vol. 59 (1), 2012, pages 247-251 0018-9383 ieexplore.ieee.org/xpl/periodicals.jsp http://hdl.handle.net/123456789/23993 en Institute of Electrical and Electronics Engineers (IEEE) |
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English |
| topic |
Drain-induced barrier lowering (DIBL) fully depleted silicon-on-insulator (FDSOI) MOSFETs ultrathin silicon body and thin buried oxide (UTBB) MASTAR model Substrate depletion depth (T Sub) Substrate/buried oxide (BOX) interface space-charge condition Ultrathin silicon body (UTB) |
| spellingShingle |
Drain-induced barrier lowering (DIBL) fully depleted silicon-on-insulator (FDSOI) MOSFETs ultrathin silicon body and thin buried oxide (UTBB) MASTAR model Substrate depletion depth (T Sub) Substrate/buried oxide (BOX) interface space-charge condition Ultrathin silicon body (UTB) Mohd Khairuddin, Md Arshad, Dr. Raskin, Jean-Pierre, Prof. Kilchytska, Valeriya, Dr. Andrieu, François, Dr. Scheiblin, Pascal Faynot, O. Flandre, Denis, Prof. Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
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Link to publisher's homepage at http://ieeexplore.ieee.org/ |
| author2 |
mohd.khairuddin@unimap.edu.my |
| author_facet |
mohd.khairuddin@unimap.edu.my Mohd Khairuddin, Md Arshad, Dr. Raskin, Jean-Pierre, Prof. Kilchytska, Valeriya, Dr. Andrieu, François, Dr. Scheiblin, Pascal Faynot, O. Flandre, Denis, Prof. |
| format |
Article |
| author |
Mohd Khairuddin, Md Arshad, Dr. Raskin, Jean-Pierre, Prof. Kilchytska, Valeriya, Dr. Andrieu, François, Dr. Scheiblin, Pascal Faynot, O. Flandre, Denis, Prof. |
| author_sort |
Mohd Khairuddin, Md Arshad, Dr. |
| title |
Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
| title_short |
Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
| title_full |
Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
| title_fullStr |
Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
| title_full_unstemmed |
Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs |
| title_sort |
extended mastar modeling of dibl in utb and utbb soi mosfets |
| publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| publishDate |
2013 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/23993 |
| _version_ |
1643794219897192448 |
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13.214268 |