An efficient modified booth multiplier architecture
Multiplier plays an important role in today’s compute intensive applications such as computer graphics and digital signal processing. This thesis described the design of an Efficient Modified Booth Multiplier Architecture. With the tradeoff between speed and area, the design of the Modified Booth...
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| 第一著者: | |
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| フォーマット: | 学位論文 |
| 言語: | English |
| 出版事項: |
Universiti Malaysia Perlis (UniMAP)
2012
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| 主題: | |
| オンライン･アクセス: | http://dspace.unimap.edu.my/xmlui/handle/123456789/20815 |
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