Design and analysis of Floating Point divider
As the advances of VLSI technology, low power design has become an important topic in VLSI design. Scaling down supply voltage is an effective way for power reduction because of its quadratic relationship to dynamic power. The objective of this project is to design and analysis of floating point d...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | Learning Object |
Language: | English |
Published: |
Universiti Malaysia Perlis
2008
|
Subjects: | |
Online Access: | http://dspace.unimap.edu.my/xmlui/handle/123456789/1972 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
id |
my.unimap-1972 |
---|---|
record_format |
dspace |
spelling |
my.unimap-19722008-09-07T03:09:00Z Design and analysis of Floating Point divider Siti Aminah Hussen Nazuhusna Khalid (Advisor) Verilog (Computer hardware description language) Printed circuits Integrated circuits -- Very large scale integration Semiconductors Floating point divider Multiplexing As the advances of VLSI technology, low power design has become an important topic in VLSI design. Scaling down supply voltage is an effective way for power reduction because of its quadratic relationship to dynamic power. The objective of this project is to design and analysis of floating point divider using Mentor Graphics tools. Mentor Graphics is an Electronic Design Automation (EDA) package. The suite of tools can handle anything from Printed Circuit Board (PCB) to Hardware Description Language(HDL). In the circuit design area, there are tools for schematic capture, digital and analog simulation, physical layout, and design verification. Many libraries contain models for popular existing design components. Floating-point divider is generally regarded as a low frequency and high latency operation in typical floating-point applications. For analysis purposes, the simulation results have been compared in terms of power consumption, delay, speed, power delay product (PDP) and layout area. Lower PDP meaning that the power is better translated into speed of operation. Floating point divider circuit consumes power is 195mWatt at 10 million operations per second. Floating point divider circuit produces 5ns delay time and 200MHz in speed. For PDP, floating point divider circuit operates 0.975ns at 10 million per second. 2008-09-07T03:09:00Z 2008-09-07T03:09:00Z 2008-04 Learning Object http://hdl.handle.net/123456789/1972 en Universiti Malaysia Perlis School of Microelectronic Engineering |
institution |
Universiti Malaysia Perlis |
building |
UniMAP Library |
collection |
Institutional Repository |
continent |
Asia |
country |
Malaysia |
content_provider |
Universiti Malaysia Perlis |
content_source |
UniMAP Library Digital Repository |
url_provider |
http://dspace.unimap.edu.my/ |
language |
English |
topic |
Verilog (Computer hardware description language) Printed circuits Integrated circuits -- Very large scale integration Semiconductors Floating point divider Multiplexing |
spellingShingle |
Verilog (Computer hardware description language) Printed circuits Integrated circuits -- Very large scale integration Semiconductors Floating point divider Multiplexing Siti Aminah Hussen Design and analysis of Floating Point divider |
description |
As the advances of VLSI technology, low power design has become an important topic in
VLSI design. Scaling down supply voltage is an effective way for power reduction because of its quadratic relationship to dynamic power. The objective of this project is to
design and analysis of floating point divider using Mentor Graphics tools. Mentor
Graphics is an Electronic Design Automation (EDA) package. The suite of tools can handle anything from Printed Circuit Board (PCB) to Hardware Description Language(HDL). In the circuit design area, there are tools for schematic capture, digital and analog
simulation, physical layout, and design verification. Many libraries contain models for popular existing design components. Floating-point divider is generally regarded as a low frequency and high latency operation in typical floating-point applications. For analysis purposes, the simulation results have been compared in terms of power consumption, delay, speed, power delay product (PDP) and layout area. Lower PDP meaning that the power is better translated into speed of operation. Floating point divider circuit consumes power is 195mWatt at 10 million operations per second. Floating point divider circuit produces 5ns delay time and 200MHz in speed. For PDP, floating point divider circuit operates 0.975ns at 10 million per second. |
author2 |
Nazuhusna Khalid (Advisor) |
author_facet |
Nazuhusna Khalid (Advisor) Siti Aminah Hussen |
format |
Learning Object |
author |
Siti Aminah Hussen |
author_sort |
Siti Aminah Hussen |
title |
Design and analysis of Floating Point divider |
title_short |
Design and analysis of Floating Point divider |
title_full |
Design and analysis of Floating Point divider |
title_fullStr |
Design and analysis of Floating Point divider |
title_full_unstemmed |
Design and analysis of Floating Point divider |
title_sort |
design and analysis of floating point divider |
publisher |
Universiti Malaysia Perlis |
publishDate |
2008 |
url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/1972 |
_version_ |
1643787509411348480 |
score |
13.19449 |