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Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities

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Bibliographic Details
Main Author: Izny Atikah Ahmad Fahmi
Other Authors: Noraini Othman (Advisor)
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis 2008
Subjects:
NMOS transistor
Metal oxide semiconductors
Integrated circuits
Negative metal oxide semiconductors (NMOS)
MOS transistor
Micro Fabrication Cleanroom
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/1368
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spelling my.unimap-13682008-07-02T08:32:29Z Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities Izny Atikah Ahmad Fahmi Noraini Othman (Advisor) NMOS transistor Metal oxide semiconductors Integrated circuits Negative metal oxide semiconductors (NMOS) MOS transistor Micro Fabrication Cleanroom Access is limited to UniMAP community. The Micro Fabrication Cleanroom in University Malaysia Perlis (UniMAp) was completed in December 2003 and was built as a teaching laboratory. The goal of this project is to simulate a 0.35um negative-metal-oxide-semiconductor (NMOS) process based on UniMAP cleanroom facilities and to study the feasibility of adopting this process using cleanroom facilities. The result of the simulation will be compared with UC Berkeley 0.35um process design in terms of the Id-Vgs characteristic. NMOS transistor will be simulated using TCAD tools that consist of Taurus TSUPREM-4 for process simulation and Taurus Medici for the device simulation. The simulation is run for UC Berkeley 0.35 nMOS transistor and the second process simulation is for 0.35 um NMOS that can fabricate in UniMAP Micro Fabrication cleanroom. For nMOS 0.35 um in UniMAP Micro Fabrication cleanroom consists of four module based on design and fabricate mask that consist four step mask layout that is source drain formation, gate formation, contact formation and metallization. The voltage threshold for UniMAP 0.35um NMOS transistor is 0.25 volts. The voltage threshold for typical NMOS process is 0.3 volts. Material parameters that effect voltage threshold, Vt includes the gate conductor material, the channel doping concentrations, the gate insulation material (SiO2) and the thickness of the gate material. 2008-07-02T08:32:29Z 2008-07-02T08:32:29Z 2007-05 Learning Object http://hdl.handle.net/123456789/1368 en Universiti Malaysia Perlis School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic NMOS transistor
Metal oxide semiconductors
Integrated circuits
Negative metal oxide semiconductors (NMOS)
MOS transistor
Micro Fabrication Cleanroom
spellingShingle NMOS transistor
Metal oxide semiconductors
Integrated circuits
Negative metal oxide semiconductors (NMOS)
MOS transistor
Micro Fabrication Cleanroom
Izny Atikah Ahmad Fahmi
Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
description Access is limited to UniMAP community.
author2 Noraini Othman (Advisor)
author_facet Noraini Othman (Advisor)
Izny Atikah Ahmad Fahmi
format Learning Object
author Izny Atikah Ahmad Fahmi
author_sort Izny Atikah Ahmad Fahmi
title Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
title_short Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
title_full Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
title_fullStr Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
title_full_unstemmed Simulation Of 0.35 Um NMOS Process Based on UniMAP Cleanroom Facilities
title_sort simulation of 0.35 um nmos process based on unimap cleanroom facilities
publisher Universiti Malaysia Perlis
publishDate 2008
url http://dspace.unimap.edu.my/xmlui/handle/123456789/1368
_version_ 1643787268446486528
score 13.214268

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