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Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics

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Bibliographic Details
Main Author: Kamarul Azman Gesly
Other Authors: Muammar Mohamad Isa (Advisor)
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis 2008
Subjects:
Mirror adder
Dynamic adder
Pipelined adder
Mentor Graphic software
Metal oxide semiconductors, Complementary
CMOS transistors
Computer arithmetic and logic units
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/1365
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spelling my.unimap-13652008-07-02T07:19:44Z Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics Kamarul Azman Gesly Muammar Mohamad Isa (Advisor) Mirror adder Dynamic adder Pipelined adder Mentor Graphic software Metal oxide semiconductors, Complementary CMOS transistors Computer arithmetic and logic units Access is limited to UniMAP community. In this project the main topology of two bit adder including the most interesting of those recently proposed, are compared for delay, power dissipation, area and power delay product (PDP) . The comparison has been performed for 2 bit adder using Mirror Adder,Dynamic Adder and Pipelined Adder configuration, the former with minimum transistor size to minimize power consumption, the latter with optimized transistor dimension to minimize power- delay product. The investigation has been carried out with properly defined simulation runs on a Mentor Graphic environment using 0.35μ tsmc technology.The design guidelines have been derived to select the most suitable topology for the design features required. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, expect for short chains of blocks or for cases where minimum power consumption is desired, topologies with transmission gates are not attractive. In contrast, the most interesting implementations in terms of trade off between power and delay are the traditional CMOS and other topologies. For analysis, pipelined is absolute have a great speed between others adders and suitable use for high-power. For speed, that compares which adder has a lowest delay according to waveform. For power dissipation, result exists in file (.chi) from test bench and power delay product out come from power dissipation multiply with delay. 2008-07-02T07:19:44Z 2008-07-02T07:19:44Z 2007-04 Learning Object http://hdl.handle.net/123456789/1365 en Universiti Malaysia Perlis School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Mirror adder
Dynamic adder
Pipelined adder
Mentor Graphic software
Metal oxide semiconductors, Complementary
CMOS transistors
Computer arithmetic and logic units
spellingShingle Mirror adder
Dynamic adder
Pipelined adder
Mentor Graphic software
Metal oxide semiconductors, Complementary
CMOS transistors
Computer arithmetic and logic units
Kamarul Azman Gesly
Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
description Access is limited to UniMAP community.
author2 Muammar Mohamad Isa (Advisor)
author_facet Muammar Mohamad Isa (Advisor)
Kamarul Azman Gesly
format Learning Object
author Kamarul Azman Gesly
author_sort Kamarul Azman Gesly
title Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
title_short Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
title_full Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
title_fullStr Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
title_full_unstemmed Comparisons of 2 Bit Mirror Adder, Dynamic Adder and Pipelined Adder Using Mentor Graphics
title_sort comparisons of 2 bit mirror adder, dynamic adder and pipelined adder using mentor graphics
publisher Universiti Malaysia Perlis
publishDate 2008
url http://dspace.unimap.edu.my/xmlui/handle/123456789/1365
_version_ 1643787267476553728
score 13.222552

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