A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility
Link to publisher's homepage at http://ieeexplore.ieee.org/
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Working Paper |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2010
|
| Subjects: | |
| Online Access: | http://dspace.unimap.edu.my/xmlui/handle/123456789/10347 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| id |
my.unimap-10347 |
|---|---|
| record_format |
dspace |
| spelling |
my.unimap-103472010-11-30T03:54:14Z A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility Mohd Azizi, Chik Ve, Chun Yung Balakrishna, Puvaneswaran Uda, Hashim, Prof. Dr. Ibrahim, Ahmad Bashir, Mohamad Cycle time Silicon wafer manufacturing plan (Fab) Simulation Work In Progress (WIP) Link to publisher's homepage at http://ieeexplore.ieee.org/ This research is to study the opportunity to achieve optimum productivity yield in 0.16μm product mixed through understanding the impact of loading utilization towards the capacity. The study is important to model the overall strategy of product loading planning to get highest achievable product output at respective time like monthly or yearly. The product mixes target used in this analysis includes 0.20um to 0.13um for high voltage, logic CMOS and also mixed signal RF. Input in analysis are list of process flow for various technologies and products, major manufacturing activities and equipment configuration that is based on actual wafer fabrication facilities systems. Part of the complexities of the research is its long cycle time process from 45minutes to 9 hours, for respective same processing step that drives from varies technology and process equipment capable. Overall cycle time is from 30 days to 90 days that is various comparing product-to-product requirements. Further added to the complexity is the equipment used for this analysis that is more than 100 difference equipment configurations. More than 50% of the equipments are with difference configuration. Most products experienced re-entranced more than 85% times to same equipment type. This analysis done on generic semiconductor fab modeled using industries software, AutoSchedAP. The fab model configured intensively so match with exactly operation of the fab, with equivalent almost 100% manufacturing operation, product loading and tool configuration. The results have been successfully developed into a curve an equation shows the optimum product loading and gives opportunity of improvement in revenue and also overall efficiency of more than 10%. Further results of this study also summarized ranges of fab utilization versus cycle time that support overall product delivery. Other impacts are also discussed in the summary. 2010-11-30T03:54:14Z 2010-11-30T03:54:14Z 2010-06-28 Working Paper p.377-380 978-1-4244-6609-2 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5549356 http://hdl.handle.net/123456789/10347 en Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE) 2010 Institute of Electrical and Electronics Engineers (IEEE) |
| institution |
Universiti Malaysia Perlis |
| building |
UniMAP Library |
| collection |
Institutional Repository |
| continent |
Asia |
| country |
Malaysia |
| content_provider |
Universiti Malaysia Perlis |
| content_source |
UniMAP Library Digital Repository |
| url_provider |
http://dspace.unimap.edu.my/ |
| language |
English |
| topic |
Cycle time Silicon wafer manufacturing plan (Fab) Simulation Work In Progress (WIP) |
| spellingShingle |
Cycle time Silicon wafer manufacturing plan (Fab) Simulation Work In Progress (WIP) Mohd Azizi, Chik Ve, Chun Yung Balakrishna, Puvaneswaran Uda, Hashim, Prof. Dr. Ibrahim, Ahmad Bashir, Mohamad A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| description |
Link to publisher's homepage at http://ieeexplore.ieee.org/ |
| format |
Working Paper |
| author |
Mohd Azizi, Chik Ve, Chun Yung Balakrishna, Puvaneswaran Uda, Hashim, Prof. Dr. Ibrahim, Ahmad Bashir, Mohamad |
| author_facet |
Mohd Azizi, Chik Ve, Chun Yung Balakrishna, Puvaneswaran Uda, Hashim, Prof. Dr. Ibrahim, Ahmad Bashir, Mohamad |
| author_sort |
Mohd Azizi, Chik |
| title |
A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| title_short |
A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| title_full |
A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| title_fullStr |
A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| title_full_unstemmed |
A study for optimum productivity yield in 0.16μm mixed of wafer fabrication facility |
| title_sort |
study for optimum productivity yield in 0.16î¼m mixed of wafer fabrication facility |
| publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| publishDate |
2010 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/10347 |
| _version_ |
1643789827459514368 |
| score |
13.222552 |