Design and implementation of advanced encryption standard using verilog HDL

• Main Authors: Shamsiah, Suhaili, Fredrick, Rene Brooke, Zainah, Md. Zain, Norhuzaimin, Julai
• Format: Conference or Workshop Item
• Language: English; English
• Published: Springer Science and Business Media Deutschland GmbH 2022
• Subjects: T Technology (General); TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://umpir.ump.edu.my/id/eprint/37557/1/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using%20verilog%20HDL.pdf; http://umpir.ump.edu.my/id/eprint/37557/2/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using_ABS.pdf; http://umpir.ump.edu.my/id/eprint/37557/; https://doi.org/10.1007/978-981-16-2406-3_37

Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the exponential development of the Internet. One of the main concerns involving software implementation of encryption algorithm is the possibility of slower processing when transmitting and receiving data which consequently will encounter low security level during process of encryption for real-time application. The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. Real-time application is essential for today’s modern world and Field Programmable Gate Array approach is applied for this purpose. The optimization approaches include loop release, pipeline architecture and Look-Up-Table (LUT) which allow for exact synchronization in order to meet applications’ requirements in real time. The design is coded using the Verilog HDL and the hardware design is analyzed and tested with Altera Cyclone II-V in Quartus II and ModelSim. Through comparative analysis with previous implementation, the maximum throughput for this design is 31.37 Gbit/s for the encryption process can operate at 244.89 MHz. The complete 128-bit AES encryption cycle requires only 41 clock cycles to get the encrypted data.