70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing

• Main Authors: Amouzad Mahdiraji, G., Abdullah, M.K., Mokhtar, M., Mohammadi, A.M., Abas, A.F., Basir, S.M., Abdullah, R.S.A.R.
• Format: Article
• Published: Photonic Network Communications 2009
• Subjects: TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/6221/; http://download.springer.com/static/pdf/333/art%253A10.1007%252Fs11107-009-0228-4.pdf?auth66=1361235549_818caaac69cd5599ea81ec73fe253b52&ext=.pdf

The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 � 10 Gb/s, the worst receiver sensit...