40 Gbit/s on-off-keyed system with 5.71 GHz clock recovery circuit using duty cycle division multiplexing

• Main Authors: Amouzad Mahdiraji, G., Malekmohammadi, A., Fauzi Abas, A., Khazani Abdullah, M.
• Format: Conference or Workshop Item
• Language: English
• Published: 2009
• Subjects: TA Engineering (General). Civil engineering (General); TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/6220/1/40_Gbits_on-off-keyed_system_with_5.71_GHz_clock_recovery_circuit_using_duty_cycle_division_multiplexing.pdf; http://eprints.um.edu.my/6220/; http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5405301

We show the realization of 40 Gbit/s on-off-keyed system that can be recovered at 5.71 GHz clock using duty cycle division multiplexing technique with the receiver sensitivity of -22.1 dBm. ©2008 Optical Society of America.