Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count

• Main Authors: Siddique, Marif Daula, Mekhilef, Saad, Shah, Noraisyah Mohamed, Sarwar, Adil, Iqbal, Atif, Tayyab, Mohammad, Ansari, Mohsin Karim
• Format: Article
• Published: Institute of Electrical and Electronics Engineers 2019
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://eprints.um.edu.my/23442/; https://doi.org/10.1109/ACCESS.2019.2925277

The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology. © 2013 IEEE.