A new parameterized architectural design for SENSE reconstruction

• 主要な著者: Siddiqui, M.F., Reza, A.W., Kanesan, J., Omer, H.
• フォーマット: Conference or Workshop Item
• 言語: English
• 出版事項: 2014
• 主題: TK Electrical engineering. Electronics Nuclear engineering
• オンライン･アクセス: http://eprints.um.edu.my/12967/1/A_New_Parameterized_Architectural.pdf; http://eprints.um.edu.my/12967/

Reconfigurable hardware based architectures that could provide good quality image reconstruction for parallel Magnetic Resonance Imaging (MRI) within very less computation time are in high demand. Hardware platforms for specific reconstruction algorithms dramatically increase the power efficiency and decrease the execution time. This research proposes a new parameterized architecture design for Sensitivity Encoding (SENSE) reconstruction. This architecture is also synthesized for Field Programmable Gate Array (FPGA). Complex multiplier, divider and complex matrix multiplier modules are designed to implement the algorithm. Furthermore, the variable data bus widths are used in the data path of the architecture, which leads to reduce the hardware cost and silicon area. Experimental results and comparisons prove the efficiency of the architecture. Moreover, in terms of computation time, the result shows that the proposed technique is 1000 times faster than the conventional MATLAB reconstruction, while maintaining the quality of the reconstructed image. The results indicate that this architectural design can prove to be a significant tool for SENSE reconstruction in MRI scanners.