Synthesis of transistor-chaining algorithm for CMOS cell layout using bipartite graph / Azizi Misnan

This project implement a algorithm for the optimal transistor chaining problem in CMOS functional cell layout based on Uehara and vanCleemput's layout style [1] which assumed that the height of each logic module layout is constant and performed the optimisation by decomposing the graph module i...

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Bibliographic Details
Main Author: Misnan, Azizi
Format: Thesis
Language:English
Published: 1997
Online Access:https://ir.uitm.edu.my/id/eprint/74388/1/74388.pdf
https://ir.uitm.edu.my/id/eprint/74388/
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