Synthesis of transistor chaining algorithm for CMOS cell layout using euler path / Sukri Hanafiah
The objective of this project is to build Optimal Layout of CMOS Functional Arrays 1C standard cell design. Firstly, this report is discussed about the Optimal Layout of CMOS Functional of CMOS functional array. Optimal Layout is the layout of the arrangment of CMOS transistor with the implementatio...
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| Format: | Thesis |
| Language: | English |
| Published: |
1997
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| Online Access: | https://ir.uitm.edu.my/id/eprint/100747/1/100747.pdf https://ir.uitm.edu.my/id/eprint/100747/ |
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