Modeling of “strain technology” on 140nm CMOS devices / Ahmad Sabirin Zoolfakar, Noor Irmahani Mohmad Tahiruddin and Lyly Nyl Ismail

• Main Authors: Zoolfakar, Ahmad Sabirin, Mohmad Tahiruddin, Noor Irmahani, Ismail, Lyly Nyl
• Format: Article
• Language: English
• Published: UiTM Press 2009
• Subjects: Electric apparatus and materials. Electric circuits. Electric networks
• Online Access: https://ir.uitm.edu.my/id/eprint/61856/1/61856.pdf; https://ir.uitm.edu.my/id/eprint/61856/; https://jeesr.uitm.edu.my/v1/

A 140nm Complementary Metal Oxide Semiconductor (CMOS) was designed and simulated to investigate stress effects on device performance. Stress can be divided into two categories which are compressive and tensile stress. Strain technology is capable to introduce stress to the CMOS devices. The strain technology can be developed by Silicon Nitride (Si3N4) capping layer, Silicide and Shallow Trench Isolation (STI). The paper discussed on the effect of strain technology on 140nm CMOS device performance focusing on threshold voltage and drain current parameters. ATHENA and ATLAS simulators were used to simulate the fabrication process and to characterize the electrical properties respectively. It can be concluded that STI is better compared to LOCOS for length gate below than 250nm devices. Compressive STI stress enhances by 13.8% PMOS performance while tensile Si3N4 capping layer improve by 1% NMOS performance. In addition CMOS with silicide module improve by 2.5% PMOS drain current.