Power efficient CMOS OTA / Nordiana Mukahar and Siti Aishah Che Kar
Research in analogue circuit design is focused on low power battery operated equipment to be used in portable equipment of electronic application. A reduced supply voltage is necessary to decrease power consumption to ensure reasonable battery lifetime in portable electronics. Realizing high perform...
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| Main Authors: | , |
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| Format: | Research Reports |
| Language: | English |
| Published: |
2012
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/52589/1/52589.pdf https://ir.uitm.edu.my/id/eprint/52589/ |
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| Summary: | Research in analogue circuit design is focused on low power battery operated equipment to be used in portable equipment of electronic application. A reduced supply voltage is necessary to decrease power consumption to ensure reasonable battery lifetime in portable electronics. Realizing high performance analogue circuit with limitation of power is a challenge. A device’s figure of merit is illustrated by the gain-bandwidth product which states that at higher frequencies, the gain decreases. Higher bias current is needed in order to have a good gain at high frequency. This shows that in general a fast circuit consumes high power and it inherent property prompts for specific techniques that can reduce power while maintaining performance. Operational Transconductance Amplifier (OTA) is a fundamental building block of analogue circuit and systems. In OTA, the ratio of transconductance to current consumption reflects the power efficiency of the amplifier and transconductance has great influence in determining the power, stability and gain of the circuit system. Improved architecture of recycle folded cascade OTA with current control circuit using transconductance based methodology has been proposed in this work. This is achieved by exploiting and using idle device in the signal path and separates the AC and DC path, which results in an enhanced transconductance, output resistance, gain, settling time and power dissipation. Recycle folded cascade amplifier architecture was implemented in 90 nm CMOS process with 1 V power supply. Simulation results shows that the proposed structure significantly increase the DC gain bandwidth compared to the recycle folded cascade OTA and consume very low power dissipation. Theoretical analysis and LTSpice simulations prove the performance of the new OTA. |
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