Electrical analysis of Si3N4 capping layer and SOI technology in Sub-65 Nm CMOS / Syed Muhamad Firdauz Syed Adrus
Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source, shallow trench isolation (STI) has not been fully utilized up to now for circuit performance improvement. In this paper, two methods have been used on 65nm...
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Format: | Student Project |
Language: | English |
Published: |
2008
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Online Access: | https://ir.uitm.edu.my/id/eprint/53894/1/53894.pdf https://ir.uitm.edu.my/id/eprint/53894/ |
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