Design consideration for successful delay fault testing in SOC

• Main Authors: Dass, Sreedharan Baskara, Hassan Abdalla Hashim, Aisha
• Format: Conference or Workshop Item
• Language: English
• Published: ICECE Publications 2004
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://irep.iium.edu.my/50147/4/50147.pdf; http://irep.iium.edu.my/50147/; http://www.buet.ac.bd/icece/pub2004/P015.pdf

Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and re...