Design and performance analysis of a fast 4-way set associative cache controller using Tree Pseudo Least Recently Used algorithm

• Main Authors: Hazlan, Mohamed Alfian Al-Zikry, Gunawan, Teddy Surya, Yaacob, Mashkuri, Kartiwi, Mira, Arifin, Fatchul
• Format: Article
• Language: English; English
• Published: Institute of Advanced Engineering and Science (IAES) Indonesia Section 2023
• Subjects: TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/110034/1/110034_Design%20and%20performance%20analysis%20of%20a%20fast%204-way.pdf; http://irep.iium.edu.my/110034/7/110034_Design%20and%20performance%20analysis%20of%20a%20fast%204-way_SCOPUS.pdf; http://irep.iium.edu.my/110034/; http://section.iaesonline.com/index.php/IJEEI/article/view/5014

In the realm of modern computing, cache memory serves as an essential intermediary, mitigating the speed disparity between rapid processors and slower main memory. Central to this study is the development of an innovative cache controller for a 4-way set associative cache, meticulously crafted using...