Design and performance analysis of a fast 4-way set associative cache controller using Tree Pseudo Least Recently Used algorithm

• Main Authors: Hazlan, Mohamed Alfian Al-Zikry, Gunawan, Teddy Surya, Yaacob, Mashkuri, Kartiwi, Mira, Arifin, Fatchul
• Format: Article
• Language: English; English
• Published: Institute of Advanced Engineering and Science (IAES) Indonesia Section 2023
• Subjects: TK7885 Computer engineering
• Online Access: http://irep.iium.edu.my/110034/1/110034_Design%20and%20performance%20analysis%20of%20a%20fast%204-way.pdf; http://irep.iium.edu.my/110034/7/110034_Design%20and%20performance%20analysis%20of%20a%20fast%204-way_SCOPUS.pdf; http://irep.iium.edu.my/110034/; http://section.iaesonline.com/index.php/IJEEI/article/view/5014

In the realm of modern computing, cache memory serves as an essential intermediary, mitigating the speed disparity between rapid processors and slower main memory. Central to this study is the development of an innovative cache controller for a 4-way set associative cache, meticulously crafted using VHDL and structured as a Finite State Machine. This controller efficiently oversees a cache of 256 bytes, with each block encompassing 128 bits or 16 bytes, organized into four sets containing four lines each. A key feature of this design is the incorporation of the Tree Pseudo Least Recently Used (PLRU) algorithm for cache replacement, a strategic choice aimed at optimizing cache performance. The effectiveness of this controller was rigorously evaluated using ModelSim, which generated a comprehensive timing diagram to validate the design's functionality, especially when integrated with a segmented main memory of four 1KB banks. The results from this evaluation were promising, showcasing precise logic outputs within the timing diagram. Operational efficiency was evidenced by the controller's swift processing speeds: read hits were completed in a mere three cycles, read misses in five and a half cycles, and both write hits and misses in three and a half cycles. These findings highlight the controller's capability to enhance cache memory efficiency, striking a balance between the complexities of set-associative mapping and the need for optimized performance in contemporary computing systems. This study not only demonstrates the potential of the proposed cache controller design in bridging the processor-memory speed gap but also contributes significantly to the field of cache memory management by offering a viable solution to the challenges posed by traditional cache configurations.