Analysis and design of low power consumption 8T and 10T full adder CMOS technology

All designers and engineers are familiar with the significance of adder subsystems. Therefore, engineers continue to perform research on them by integrating creative design ideas to boost the speed of the circuit and decrease its power consumption. In numerous digital data processing applications,...

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Main Authors: Abd Majid, Mohamed Ibrahim, Sahak, Rohilah, Subramaniam, Krishnan, Zainuddin, Ahmad Anwar, Abdul Rahman, Siti Husna, Ahmad Puzi, Asmarani, Mohd Mansor, Ahmad Fairuzabadi, Mohamad Yunos, Muhammad Farhan Affendi, Svpk, Satya Devu
Format: Conference or Workshop Item
Language:English
Published: Institute of Electrical and Electronics Engineers (IEEE) 2022
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Online Access:http://irep.iium.edu.my/101594/1/101594_Analysis%20and%20design%20of%20low%20power%20consumption.pdf
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https://ieeexplore.ieee.org/document/9946570
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spelling my.iium.irep.1015942022-12-05T07:05:31Z http://irep.iium.edu.my/101594/ Analysis and design of low power consumption 8T and 10T full adder CMOS technology Abd Majid, Mohamed Ibrahim Sahak, Rohilah Subramaniam, Krishnan Zainuddin, Ahmad Anwar Abdul Rahman, Siti Husna Ahmad Puzi, Asmarani Mohd Mansor, Ahmad Fairuzabadi Mohamad Yunos, Muhammad Farhan Affendi Svpk, Satya Devu TK7885 Computer engineering All designers and engineers are familiar with the significance of adder subsystems. Therefore, engineers continue to perform research on them by integrating creative design ideas to boost the speed of the circuit and decrease its power consumption. In numerous digital data processing applications, such as microprocessors, and digital signal processors, adder logic cells are utilized. To implement Complementary Metal Oxide Semiconductor (CMOS) design techniques, many logic styles are employed. One example is the full adder, which is at the heart of every central processing unit and is essential to the way every type of computer processor works. In this paper, a design of 8 transistors and 10 transistors was developed using DSCH 3.5. Full adders are fundamental components of the ALU, which is the microprocessors' and Digital Signal Processing's logical and arithmetic unit. The Micro wind 3.5 tool is used to conduct simulation of the generated full adder design while operating at room temperature. The proposed 8T design shows 71.742µW power consumption, the time delay is 0.880ns and has 1.15 GHZ speed. The 10T design has less power consumption than 8T design. According to the findings of the investigation, the 8T design demonstrates superior speed efficiency and reduced power consumption when compared to the 10T design methodologies that were taken into consideration. Institute of Electrical and Electronics Engineers (IEEE) 2022-11-22 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/101594/1/101594_Analysis%20and%20design%20of%20low%20power%20consumption.pdf Abd Majid, Mohamed Ibrahim and Sahak, Rohilah and Subramaniam, Krishnan and Zainuddin, Ahmad Anwar and Abdul Rahman, Siti Husna and Ahmad Puzi, Asmarani and Mohd Mansor, Ahmad Fairuzabadi and Mohamad Yunos, Muhammad Farhan Affendi and Svpk, Satya Devu (2022) Analysis and design of low power consumption 8T and 10T full adder CMOS technology. In: 2022 IEEE 13th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), Vancouver, BC, Canada. https://ieeexplore.ieee.org/document/9946570 10.1109/IEMCON56893.2022.9946570
institution Universiti Islam Antarabangsa Malaysia
building IIUM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider International Islamic University Malaysia
content_source IIUM Repository (IREP)
url_provider http://irep.iium.edu.my/
language English
topic TK7885 Computer engineering
spellingShingle TK7885 Computer engineering
Abd Majid, Mohamed Ibrahim
Sahak, Rohilah
Subramaniam, Krishnan
Zainuddin, Ahmad Anwar
Abdul Rahman, Siti Husna
Ahmad Puzi, Asmarani
Mohd Mansor, Ahmad Fairuzabadi
Mohamad Yunos, Muhammad Farhan Affendi
Svpk, Satya Devu
Analysis and design of low power consumption 8T and 10T full adder CMOS technology
description All designers and engineers are familiar with the significance of adder subsystems. Therefore, engineers continue to perform research on them by integrating creative design ideas to boost the speed of the circuit and decrease its power consumption. In numerous digital data processing applications, such as microprocessors, and digital signal processors, adder logic cells are utilized. To implement Complementary Metal Oxide Semiconductor (CMOS) design techniques, many logic styles are employed. One example is the full adder, which is at the heart of every central processing unit and is essential to the way every type of computer processor works. In this paper, a design of 8 transistors and 10 transistors was developed using DSCH 3.5. Full adders are fundamental components of the ALU, which is the microprocessors' and Digital Signal Processing's logical and arithmetic unit. The Micro wind 3.5 tool is used to conduct simulation of the generated full adder design while operating at room temperature. The proposed 8T design shows 71.742µW power consumption, the time delay is 0.880ns and has 1.15 GHZ speed. The 10T design has less power consumption than 8T design. According to the findings of the investigation, the 8T design demonstrates superior speed efficiency and reduced power consumption when compared to the 10T design methodologies that were taken into consideration.
format Conference or Workshop Item
author Abd Majid, Mohamed Ibrahim
Sahak, Rohilah
Subramaniam, Krishnan
Zainuddin, Ahmad Anwar
Abdul Rahman, Siti Husna
Ahmad Puzi, Asmarani
Mohd Mansor, Ahmad Fairuzabadi
Mohamad Yunos, Muhammad Farhan Affendi
Svpk, Satya Devu
author_facet Abd Majid, Mohamed Ibrahim
Sahak, Rohilah
Subramaniam, Krishnan
Zainuddin, Ahmad Anwar
Abdul Rahman, Siti Husna
Ahmad Puzi, Asmarani
Mohd Mansor, Ahmad Fairuzabadi
Mohamad Yunos, Muhammad Farhan Affendi
Svpk, Satya Devu
author_sort Abd Majid, Mohamed Ibrahim
title Analysis and design of low power consumption 8T and 10T full adder CMOS technology
title_short Analysis and design of low power consumption 8T and 10T full adder CMOS technology
title_full Analysis and design of low power consumption 8T and 10T full adder CMOS technology
title_fullStr Analysis and design of low power consumption 8T and 10T full adder CMOS technology
title_full_unstemmed Analysis and design of low power consumption 8T and 10T full adder CMOS technology
title_sort analysis and design of low power consumption 8t and 10t full adder cmos technology
publisher Institute of Electrical and Electronics Engineers (IEEE)
publishDate 2022
url http://irep.iium.edu.my/101594/1/101594_Analysis%20and%20design%20of%20low%20power%20consumption.pdf
http://irep.iium.edu.my/101594/
https://ieeexplore.ieee.org/document/9946570
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score 13.160551