DESIGNING LOW VOLTAGE AND POWER CMOS OP AMP

• Main Author: Yusoff, Mohd Ridzuan
• Format: Final Year Project
• Language: English
• Published: Universiti Teknologi PETRONAS 2007
• Subjects: TK Electrical engineering. Electronics Nuclear engineering
• Online Access: http://utpedia.utp.edu.my/9677/1/2007%20-Designing%20Low%20Voltage%20And%20Power%20CMOS%20OP%20AMP.pdf; http://utpedia.utp.edu.my/9677/

The importance of using low supply voltage for analogue circuit has enormously increased in recent past. The recent trend shows that a supply voltage can be degraded until 1.5 V. Low power consumption also important to increase the battery life, the packaging density and circuit reliability. CMOS op amp technology today can have power consumption lower than 200 uW. The objective of this project is to design low supply voltage and low power consumption CMOS operational amplifier. Low supply voltage op amp with 1.6 V has been successfully designed. The design was using bulk-driven PMOS transistors as an input differential of the op amp. The compensation capacitor was also used to control the power consumption. The op amp is capable of producing low power consumption of 20 uAV. The layout was design using 0.35 urn technology and have gone through DRC and LVS check. Software Virtuoso Schematic Capture and Virtuoso Spectre Circuit Simulator from cadence have been used for schematic capture and design simulation. For layout design, DRC and LVS check, softwere Calibre from Mentor Graphic have been used. IV